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janwas
c50505f54c
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
...
This was SVN commit r2722.
2005-09-14 16:58:10 +00:00
..
unix
…
win
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
2005-09-14 16:58:10 +00:00
cpu.h
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
2005-09-14 16:58:10 +00:00
dir_watch.h
…
gfx.h
…
ia32.asm
…
ia32.cpp
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
2005-09-14 16:58:10 +00:00
ia32.h
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
2005-09-14 16:58:10 +00:00
os.h
…
snd.h
…
sysdep.cpp
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
2005-09-14 16:58:10 +00:00
sysdep.h
read intel doc on multicore, realized it'd break our #cpu detect (which is actually critical because it determines safety of TSC). wrote new CPU detect code which should fix it (wasn't easy, grr); cannot test for lack of Pentium EE hardware ;p
2005-09-14 16:58:10 +00:00