diff --git a/source/lib/sysdep/arch/x86_x64/msr.cpp b/source/lib/sysdep/arch/x86_x64/msr.cpp
index b7f14c357e..7eb08d772c 100644
--- a/source/lib/sysdep/arch/x86_x64/msr.cpp
+++ b/source/lib/sysdep/arch/x86_x64/msr.cpp
@@ -63,7 +63,7 @@ bool HasEnergyPerfBias()
 }
 
 
-bool HasNehalem()
+bool HasPlatformInfo()
 {
 	if(x86_x64_Vendor() != X86_X64_VENDOR_INTEL)
 		return false;
@@ -73,13 +73,49 @@ bool HasNehalem()
 
 	switch(x86_x64_Model())
 	{
-	// Nehalem (documented in 253669-035US B.4.1)
+	// Xeon 5500 / i7 (section B.4 in 253669-037US)
 	case 0x1A:	// Bloomfield, Gainstown
 	case 0x1E:	// Clarksfield, Lynnfield, Jasper Forest
 	case 0x1F:
 		return true;
 
-	// Westmere (documented in 253669-035US B.5)
+	// Xeon 7500 (section B.4.2)
+	case 0x2E:
+		return true;
+
+	// Xeon 5600 / Westmere (section B.5)
+	case 0x25:	// Clarkdale, Arrandale
+	case 0x2C:	// Gulftown
+		return true;
+
+	// Xeon 2xxx / Sandy Bridge (section B.6)
+	case 0x2A:
+	case 0x2D:
+		return true;
+
+	default:
+		return false;
+	}
+}
+
+
+bool HasUncore()
+{
+	if(x86_x64_Vendor() != X86_X64_VENDOR_INTEL)
+		return false;
+
+	if(x86_x64_Family() != 6)
+		return false;
+
+	switch(x86_x64_Model())
+	{
+	// Xeon 5500 / i7 (section B.4.1 in 253669-037US)
+	case 0x1A:	// Bloomfield, Gainstown
+	case 0x1E:	// Clarksfield, Lynnfield, Jasper Forest
+	case 0x1F:
+		return true;
+
+	// Xeon 5600 / Westmere (section B.5)
 	case 0x25:	// Clarkdale, Arrandale
 	case 0x2C:	// Gulftown
 		return true;
diff --git a/source/lib/sysdep/arch/x86_x64/msr.h b/source/lib/sysdep/arch/x86_x64/msr.h
index 2409a3063c..626f6166f2 100644
--- a/source/lib/sysdep/arch/x86_x64/msr.h
+++ b/source/lib/sysdep/arch/x86_x64/msr.h
@@ -44,19 +44,22 @@ enum ModelSpecificRegisters
 	IA32_PERF_GLOBAL_CTRL       = 0x38F,
 	IA32_PERF_GLOBAL_OVF_CTRL   = 0x390,
 
-	// Nehalem (requires HasNehalem)
-	NHM_PLATFORM_INFO               = 0x0CE,
-	NHM_UNCORE_PERF_GLOBAL_CTRL     = 0x391,
-	NHM_UNCORE_PERF_GLOBAL_STATUS   = 0x392,
-	NHM_UNCORE_PERF_GLOBAL_OVF_CTRL = 0x393,
-	NHM_UNCORE_PMC0                 = 0x3B0,
-	NHM_UNCORE_PERFEVTSEL0          = 0x3C0
+	// Nehalem and later
+	PLATFORM_INFO               = 0x0CE,	// requires HasPlatformInfo
+
+	// Nehalem, Westmere (requires HasUncore)
+	UNCORE_PERF_GLOBAL_CTRL     = 0x391,
+	UNCORE_PERF_GLOBAL_STATUS   = 0x392,
+	UNCORE_PERF_GLOBAL_OVF_CTRL = 0x393,
+	UNCORE_PMC0                 = 0x3B0,
+	UNCORE_PERFEVTSEL0          = 0x3C0
 };
 
 LIB_API bool IsAccessible();
 
 LIB_API bool HasEnergyPerfBias();
-LIB_API bool HasNehalem();
+LIB_API bool HasPlatformInfo();
+LIB_API bool HasUncore();
 
 LIB_API u64 Read(u64 reg);
 LIB_API void Write(u64 reg, u64 value);
diff --git a/source/lib/sysdep/os/win/whrt/tsc.cpp b/source/lib/sysdep/os/win/whrt/tsc.cpp
index 491bebfb44..ca2efa4975 100644
--- a/source/lib/sysdep/os/win/whrt/tsc.cpp
+++ b/source/lib/sysdep/os/win/whrt/tsc.cpp
@@ -222,9 +222,9 @@ public:
 		// clock is subject to thermal drift and would require continual
 		// recalibration anyway.
 #if ARCH_X86_X64
-		if(MSR::IsAccessible() && MSR::HasNehalem())
+		if(MSR::IsAccessible() && MSR::HasPlatformInfo())
 		{
-			const u64 platformInfo = MSR::Read(MSR::NHM_PLATFORM_INFO);
+			const u64 platformInfo = MSR::Read(MSR::PLATFORM_INFO);
 			const u8 maxNonTurboRatio = bits(platformInfo, 8, 15);
 			return maxNonTurboRatio * 133.33e6f;
 		}